In electronic devices, a clock signal that oscillates from a high state to a low state is used to coordinate the timing of two or more electronic circuits. Several electronic circuits can be coordinated together by feeding a common clock signal to each of the several circuits, synchronizing the rising and falling edges of the clock signal at each circuit, and then coordinating the circuits' timing based on the rising and/or falling edges of the common clock signal. The relative timing of the rising and falling edges of a clock signal is referred to as a “duty cycle”. Typically, the rising edge and falling edge of a clock signal are separated by equal periods of time, resulting in a duty cycle of 50%.
As electronic devices are designed to run at faster speeds, the clock signals on the devices must oscillate at higher frequencies, where small amounts of signal distortion can significantly affect the duty cycle of the clock signal. As a result, electronic circuits in high speed devices often incorporate circuitry that corrects the distortion in a received clock signal in order to ensure accurate synchronization.
FIG. 1 shows a conventional Single-Ended Duty Cycle Correction (SEDCC) circuit 100 that is used to compensate for duty cycle distortion in a clock signal. The SEDCC circuit 100 includes a delay cell 102 that receives an input clock signal 104 through a buffer 108. The delay cell 102 introduces a delay to one of the two edges of the input clock signal 104 (i.e. rising edge or falling edge) based upon a DC error feedback signal 120. The delay cell 102 outputs an output clock signal 106 through two additional buffers 110 and 112. Since delay of only one edge of the input signal 104 is adjusted and that of the other edge is fixed, the time from a rising edge to the next falling edge will be adjusted. Thus, the delay introduced by the delay cell 102 causes the output clock signal 106 to have a different duty cycle than the input clock signal 104.
The SEDCC circuit 100 further includes a feedback loop that includes a feedback buffer 114, an RC filter 116 and an amplifier 118. The output clock signal 106 is received by the RC filter 116, through the feedback buffer 114. The RC filter 110 converts the output clock signal 106 to a DC averaged clock signal 122, which is input to an amplifier 118. The amplifier 118 compares the DC averaged clock signal 122 to a reference DC voltage of ½ Vdd and generates a DC error feedback signal 120 based on the voltage offset between the DC averaged clock signal 122 and ½ Vdd. The DC error feedback signal 120 is, therefore, based on the difference between the duty cycle of the output clock signal 106 and 50%. The delay cell 102 adjusts the duty cycle of output clock signal 106 based on the DC error feedback signal 120 in order to reduce the DC error feedback signal 120 to zero and achieve a 50% duty cycle in the adjusted clock signal 106.
FIG. 2 shows a circuit level diagram of the feedback buffer 114 and the RC filter 1 16 of FIG. 1. The feedback buffer 114 includes a PMOS device 150 and an NMOS device 152. The feedback buffer 114 receives the output clock signal 106 as input and transmits a buffered output clock signal 154 as output. When the output clock signal 106 is at a logic high level, the PMOS device 150 turns off and the NMOS device 152 turns on, pulling the buffered output clock signal 154 down to ground and giving the PMOS device 150 an effective resistance of Rp. When the adjusted clock signal 106 is at a logical low level, the NMOS device 152 turns off an the PMOS device 150 turns on, pulling the buffered output clock signal 154 up to Vdd and giving the NMOS device 152 an effective resistance of Rn. The RC filter 116 converts the buffered output clock signal 154 to the DC averaged clock signal 122.
A drawback of the SEDCC circuit 100 is that, in practice, a mismatch in the effective resistances of the NMOS device 152 and the PMOS device 150 of the buffer 114 may cause a variation in the DC averaged clock signal 122. As a result, when the duty cycle of the output clock signal 106 reaches 50%, the DC averaged clock signal 122 is offset higher or lower than ½ Vdd. The offset causes the DC error feedback signal 120 to have a non-zero value in response to a perfect clock signal, in response to which the delay cell 102 adjusts the duty cycle of output clock signal 106 away from the desired 50%.